Concurrency

Mon, 01 Jan 0001 00:00:00 +0000

Concurrent programs must behave correctly across many possible interactions between threads and processes. Bugs can depend on rare schedules, subtle synchronization patterns, or the memory model of the underlying language and hardware. We develop algorithms and tools that make these behaviors easier to explore, understand, and verify.

Our work connects the mathematical foundations of concurrency with practical program analysis. We study both the complexity of verification problems and techniques that scale to real executions.

Research directions

Memory models and language semantics. Understanding weak memory and message-passing concurrency, and developing rigorous semantics for concurrent programming languages such as Go.
Testing, runtime verification, and predictive analysis. Finding concurrency bugs through fuzzing and schedule exploration, monitoring correctness conditions such as linearizability, and predicting errors from observed executions.
Formal verification. Developing proof techniques and automated methods for establishing the correctness of concurrent programs and distributed protocols.

Selected publications

Dynamic Race Detection with O(1) Samples. CACM 2026.
Greybox Fuzzing for Concurrency Testing. ASPLOS 2024.
How Hard Is Weak-Memory Testing?. POPL 2024.

All projects

Formal Methods for Secure Hardware Design

Mon, 01 Jan 0001 00:00:00 +0000

Hardware designs combine concurrent components whose correctness depends on precise timing and communication. Subtle mistakes in these interactions can undermine both functional correctness and security. We investigate how programming languages and formal methods can make hardware easier to design, compose, and verify.

A central part of this work is Anvil, a hardware description language that uses a type system to prevent timing hazards. Anvil makes timing relationships explicit and checks contracts between communicating modules, while retaining control over cycle-level timing and supporting dynamic timing behavior.

Research directions

Safe hardware languages. Designing abstractions and type systems that make timing and communication requirements explicit and checkable.
Compositional verification. Reasoning about individual modules and the contracts needed for their safe composition into larger designs.
Secure hardware design. Developing foundations and tools for expressing and checking security requirements alongside functional correctness.
Translation and tool support. Exploring how existing hardware designs can be translated into safer languages, with type checking, testing, simulation, and formal verification helping to validate the result.

Selected publication

Anvil: A General-Purpose Timing-Safe Hardware Description Language. ASPLOS 2026.

All projects

Projects | FOCS Lab @ NUS

Concurrency

Research directions

Selected publications

Formal Methods for Secure Hardware Design

Research directions

Selected publication